Reliably transmitting data at high speeds, e.g. between a DRAM device and a memory controller, requires the IO drivers to ensure that the required electrical signaling levels are achieved. On-chip process, voltage and temperature variations can alter the electrical characteristics of the IO driver circuit, resulting in deviations from the desired signaling levels. Deviations in the signaling levels result in reduced timing and voltage margins and therefore in lower data transmission rates, reduced signal integrity and increased power consumption.
From, e.g., U.S. Pat. No. 7,969,181 B1 it is known to use an external resistor as a reference impedance and a calibration circuit to control the impedance of the IO driver to match this reference impedance. A monitoring circuit monitors the driver output and a control circuit adjusts the impedance of the output driver in dependence of the monitoring result.
When one IO pad is spent to calibrate one corresponding reference IO driver cell this way, the other IO driver cells, similar to the first one, can be adjusted to the same required impedance value (see FIG. 1). However, when the IO driver consists of, e.g., a mix of different types of transistors and/or transistor types with high on-chip variation such an approach may not be optimal. Accordingly, it is desired to ensure high frequency signaling while avoiding impedance mismatches in an alternative way.